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rev.2.00, jul.16.2004, page 1 of 13 HD151012 8-bit binary programmable counter with synchronous preset enable rej03d0299?0200z (previous ade-205-132 (z)) preliminary rev.2.00 jul.16.2004 description the HD151012 has 8-bit binary down counter and d-type flip flop. the counter can set up to max 256 counts and synchronous preset ( spe ) input can preset the data. when the count value is 0, the next clock pulse presets the data to invert the output. d-type flip flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge. it is applied to generate ac signal for stn type liquid crystal and general-use divider. features ? high speed operation tpd (clk or clk to q) = 35 ns (typ) ? high output current fanout of 10 ls ttl loads ? wide operating voltage v cc = 2 to 6 v ? low supply current (ta = 25c) i cc (static) = 4 a (max) ? ordering information part name package type package code package abbreviation taping abbreviation (quantity) HD151012tell tssop-16 pin ttp-16dav t ell (2,000 pcs/reel) function table control inputs clr pr spe spe spe spe mode operation description h h h generally count down count at the rise edge of clock (clk) down count at the fall edge of clock (clk) x x l synchronous preset jn data is preset at the rise of clock (clk), the fall of clock (clk) l h ? initialize of q output initialize of q = ?l? h l ? initialize of q output initialize of q = ?h? notes: 1. synchronous preset ( spe ) input can set max 256 down counts. 2. when the count value is 0, the next clock pulse presets the data to invert the output. 3. clr and pr inputs initialize output state. h : high level l : low level x : immaterial ? : irrespective of condition
HD151012 rev.2.00, jul.16.2004, page 2 of 13 pin arrangement 11 12 13 14 v cc 1 2 3 4 5 6 7 10 gnd (top view) 8 9 15 16 j 0 j 1 j 2 j 3 j 4 j 5 j 6 clk clk q pr spe clr j 7 pin description pin name pin description input pins j0 to j7 count data input for option clk, clk clock inputs clk : rise edge trigger clk : fall edge trigger spe preset input for jn data pr preset input for d-type flip flop (initialize ?l? at q output) clr clear input for d-type flip flop (initialize ?h? at q output) output pins q output for d-type flip flop absolute maximum ratings item symbol ratings unit supply voltage v cc ?0.5 to 7.0 v input / output voltage v in /v out ?0.5 to v cc +0.5 v vcc, gnd current i cc , ignd 50 ma output current / pin i out 25 ma power dissipation p t 500 mw storage temperature tstg ?65 to 150 c input diode current i ik 20 ma output diode current i ok 20 ma notes: 1. the absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. all voltage values except for differential input voltage are with respect to network ground terminal.
HD151012 rev.2.00, jul.16.2004, page 3 of 13 recommended operating conditions item symbol min typ max unit supply voltage v cc 2?6v input/output voltage v in / out 0?v cc v operating temperature topr ?40 ? +85 c input rise/fall time * 1 v cc = 2.5 v t r , t f 0 ? 1000 ns v cc = 4.5 v 0 ? 500 v cc = 5.5 v 0 ? 400 note: 1. this item guarantees maximum limit when one input switches. logic diagram clk clk clk 8-bit binary counter spe pr clr pr d ck q q clr q co spe j0 j0 j1 j1 j2 j2 j3 j3 j4 j4 j5 j5 j6 j6 j7 j7
HD151012 rev.2.00, jul.16.2004, page 4 of 13 electrical characteristics ta = 25c ta = ?40 to 85c item symbol v cc min typ max min max unit test conditions high level input v ih 2.0 1.5 ? ? 1.5 ? v j0 to j7 voltage 4.5 3.15 ? ? 3.15 ? spe 6.0 4.2 ? ? 4.2 ? pr, clr 2.0 1.5 ? ? 1.5 ? clk , clk 4.5 3.15 ? ? 3.15 ? 6.0 4.2 ? ? 4.2 ? low level input v il 2.0 ? ? 0.5 ? 0.5 v j0 to j7 voltage 4.5 ? ? 1.35 ? 1.35 spe 6.0 ? ? 1.8 ? 1.8 pr, clr 2.0??0.5?0.5 clk , clk 4.5 ? ? 1.35 ? 1.35 6.0??1.8?1.8 high level output v oh 2.0 1.9 2.0 ? 1.9 ? v v in =i oh = ?20 ma voltage 4.5 4.4 4.5 ? 4.4 ? v ih or v il 6.0 5.9 6.0 ? 5.9 ? 4.5 4.18 4.31 ? 4.13 ? i oh = ?4 ma 6.0 5.68 5.80 ? 5.63 ? i oh = ?5.2 ma low level output v ol 2.0 ? 0.0 0.1 ? 0.1 v v in =i ol = 20 ma voltage 4.5 ? 0.0 0.1 ? 0.1 v ih or v il 6.0 ? 0.0 0.1 ? 0.1 4.5 ? 0.17 0.26 ? 0.33 i ol = 4 ma 6.0 ? 0.18 0.26 ? 0.33 i ol = 5.2 ma input capacitance i in 6.0 ? ? 0.1 ? 1.0 ma v in = v cc or gnd supply current i cc 6.0 ? ? 4.0 ? 40.0 ma v in = v cc or gnd
HD151012 rev.2.00, jul.16.2004, page 5 of 13 switching characteristics (c l = 50 pf, t r = t f = 6 ns) sym- ta = 25c ta = ?40 to 85c item bol v cc min typ max min max unit test conditions maximum clock f max 2.0??4 ?3 mhz frequency 4.5 ? 36 20 ? 16 6.0 ? ? 24 ? 19 output rise/fall time t tlh 2.0 ? 30 75 ? 95 ns t thl 4.5 ? 8 15 ? 19 6.0 ? 7 13 ? 16 propagation delay t plh 2.0 ? ? 300 ? 380 clk or clk to q time t phl 4.5 ? 35 60 ? 75 6.0 ? ? 53 ? 65 t plh 2.0 ? ? 150 ? 185 pr or clr to q t phl 4.5 ? 18 30 ? 38 6.0 ? ? 25 ? 32 pulse width tw 2.0 80 ? ? 100 ? ns (clk, clk , pr, clr) 4.5 16 ? ? 20 ? 6.014??17? setup time ts 2.0 100 ? ? 125 ? ns (jn - clk, clk ) 4.520??25? ( spe , clk, clk ) 6.017??21? hold time th 2.0 15 ? ? 15 ? ns (jn - clk, clk ) 4.510??10? ( spe , clk, clk ) 6.05 ??5 ? input capacitance c in ? ? 5 10 ? 10 pf power dissipation capacitance * 1 c pd ??48???pf note: 1. cpd is equivalent capacitance inside of the ic calculated from the operating current without load (see test circuit). the average operating current without load is calculated according to the expression below. i cc (opr) = c pd ? v cc ? f in + i cc
HD151012 rev.2.00, jul.16.2004, page 6 of 13 test circuit v cc v cc j0 see function table pulse generator z = 50 out pulse generator z = 50 out ? ? j1 j7 clk clk spe pr clr c l q output input input note: 1. c l includes probe and jig capacitance. waveforms ? 1 clk 10 % 90 % 50 % 50 % 90 % 6 ns 6 ns 10 % t w t w v cc gnd clk q t plh 90 % 10 % 50 % t tlh v oh v ol 90 % 10 % 50 % t thl t phl
HD151012 rev.2.00, jul.16.2004, page 7 of 13 waveforms ? 2 jn v cc gnd v cc v oh v ol 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 50 % 10 % clk gnd t s 50 % clk f/f output internal delay * 1 50 % 6 ns waveforms ? 3 jn v cc gnd v cc v oh v ol 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 50 % 10 % clk gnd t h 50 % internal delay clk * 1 f/f output 6 ns 50 % note: 1. f/f output is internal signal of ic.
HD151012 rev.2.00, jul.16.2004, page 8 of 13 waveforms ? 4 spe v cc gnd v cc v oh v ol 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % 50 % clk gnd t s 50 % internal delay clk f/f output 50 % 6 ns * 1 waveforms ? 5 internal delay spe v cc gnd v cc v oh v ol 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % 50 % clk gnd t h 50 % clk f/f output 6 ns 50 % * 1 note: 1. f/f output is internal signal of ic.
HD151012 rev.2.00, jul.16.2004, page 9 of 13 waveforms ? 6 clr pr q v oh v ol 90 % v cc gnd 50 % 10 % t f t r 90 % 50 % 10 % v cc gnd 90 % 50 % 10 % t f t r 90 % 50 % 10 % 50 % t phl 50 % t w t w t plh
HD151012 rev.2.00, jul.16.2004, page 10 of 13 timing chart clk spe j0 j1 j2 j3 j4 j5 j6 j7 (co=spe) clr q pr q count 543210321035 34 (initialize of clr) (initialize of pr)
HD151012 rev.2.00, jul.16.2004, page 11 of 13 example of application circuit ac signal generator for stn type liquid crystal panel initialize counter: 50 v cc gnd j 0 j 1 j 2 j 3 j 4 j 5 j 6 clk clk q pr spe clr j 7 * * note: when initializing output d-f/f apply ?l?
HD151012 rev.2.00, jul.16.2004, page 12 of 13 timing chart example of ac signal generator clk spe j0 j1 j2 j3 j4 j5 j6 j7 (co=spe) clr q pr q count 50 50 49 48 2 1 0 50 1 0 50 49 1 2 3 49 50 51 52 53 101 102 103 104 49
HD151012 rev.2.00, jul.16.2004, page 13 of 13 package dimensions package code jedec jeita mass (reference value) ttp-16dav ? ? 0.05 g *ni/pd/au plating 0.50 ?0.10 0? ?8? *0.15 ?0.05 6. 40 ?0.20 0.10 1.10 max 0.13 m 0.65 18 16 9 4.40 5.00 5.30 max 0.07 +0.03 0.04 0.65 max 1.0 * 0.20 ?0.05 as of january, 2003 unit: mm
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